Now There’s a Faster and Easier Way to Debug your PCIe® Designs.
Our new white paper will show you why something new is needed for testing margins in PCI Express designs. Read about current methods and the new class of test and measurement product for PCIe Gen 3 and Gen 4 margin testing: the TMT4 Margin Tester. Then ask to speak to a sales engineer about your application.
Fast, Easy PCIe Lane Margining
The TMT4 Margin Tester’s targeted Tx/Rx capability allows you to capture issues with PCIe Gen 3 and Gen 4 communications on both ends of the link and enables teams to evaluate the link health of up to x16 Gen 4 links, across all PCIe presets 0-9, in minutes. Simple to setup, configure and use, it enables a broad team to quickly assess the health of the link formed between Margin Tester and their DUT.
